1. Field of the Invention
This invention relates to semiconductor switches, and in particular to semiconductor switches for microwave as well as millimeter wave bands using a transmission line comprising a dielectric substance substrate and metal conductors, and diodes or field effect transistors (FETs) showing distributed parameter effect.
2. Description of the Prior Art
As a semiconductor switching circuit which is contemplated for use in microwave as well as millimeter wave bands, in particular with high frequencies not less than 60 GHz, various kinds of circuits have been proposed and manufactured for trial.
Single-pole 3-throw (SP3T) switches for the 77 GHz band (hereinafter to be referred to as Conventional example 1) were reported by M. Case et al. in “1997 MTT-S IMS Digest pp. 1047–1050” and can be nominated as an example of conventional switches.
An SP3T switch of Conventional example 1 comprises configuration as shown in FIG. 12. An input terminal 20 is connected with a signal junction N via a transmission line 21. One end of each transmission line 22–24 having length of a quarter of propagating wave length (a quarter wave length transmission line) is connected via capacitance C1, C2, and C3 for DC cutting respectively to each signal junction. The other end of each of a quarter wave length transmission lines 22–24 is connected respectively to one end of PIN diode D1, D2, or D3 as well as to the first, the second, or third output terminal 25–27. The other end of each PIN diode D1, D2, or D3 is connected with the earth. Capacitance C1, C2, and C3 for DC cutting, a quarter wave length transmission lines 22–24, diodes D1, D2, and D3, and the first, the second, and the third output terminals 25–27 form three output signal passes.
A diode can be expressed as a resistance for equivalent circuit thereof when the diode is biased forward, and can be expressed as a capacitance for equivalent circuit thereof when the diode is biased in the reverse direction. Accordingly, when a diode is biased forward, there exists little impedance, and the anode and cathode thereof may be regarded to be short-circuited. In addition, the impedance for frequencies in correspondence with propagating wave length when this diode is seen via a quarter wave length transmission line is close to infinite, and thus may be regarded as almost open. That is, a signal pass where a diode is biased forward will be seen as almost open from the signal junction, and as a consequence, an RF signal having propagated the signal pass will be almost totally reflected. On the other hand, since a diode which is biased in the reverse direction functions as a capacitance, the impedance will get high for low frequencies, and accordingly a signal pass where a diode is biased in the reverse direction is transparent. As the frequency gets higher, the impedance of a capacitance gets lower, and therefore, signal reflection at a signal junction will increase. As a result, a signal pass where a diode is biased in the reverse direction allows signals to travel transparently, but on the other hand, an increase in frequency will result in an increase in loss due to reflection.
Thus, in switches of Conventional example 1, among the three output signal passes, the signal pass to make signals travel transparently comprises a diode, which is biased in the reverse direction, and on the other hand, the other remaining signal passes comprise diodes, which are biased forward, to cut off signals on the other remaining signal passes, which will enable to switch the signal passes.
Insertion loss as well as isolation in a single-pole single-throw (SPST) of Conventional example 1 as described above can for the purpose of simplicity be supposed that characteristic impedance of the transmission line equals impedance of the input-output terminals, and then can be expressed as the equation (1) and the equation (2).
                    IL        =                  4                      4            +                                          ω                2                            ⁢                              C                2                            ⁢                              Z                0                2                                                                        (        1        )                                          I          SO                =                  4                      (                          2              +                                                Z                  0                                R                                      )                                              (        2        )            
As apparent from the equation (2), isolation is expressed with the resistance R and the impedance Z0 of the input-output terminals, but does not depend on frequencies. In switches of Conventional example 1, however, when isolation of, for example, not less than 40 dB is to be attained, the resistance values of diode will have to be not more than 0.13 Ω. Here, in the disclosed document of Conventional example 1, the resistance value of the diode is described as 3 Ω. Accordingly, in switches of Conventional example 1, for the purpose of realizing a resistance value of 0.13 Ω, the anode electrode area to be multiplied approximately by 23 will do. However, the anode electrode area being 23 times as much means that the capacitance value will simultaneously be 23 times as much as well. As a result, since the capacitance value of the diode disclosed in the document is 33 fF, the capacitance to attain isolation of 40 dB will be 759 fF which is 23 times as much. Based on this, with reference to the equation (1), insertion loss for a capacitance of 33 fF (=33×10−15 F) is 0.6 dB, while insertion loss reaches as much as 19 dB when the anode electrode area is made 23 times as much. That is, in switching circuit of the above-described Conventional example 1, insertion loss and isolation are in a trade-off relationship, and high isolation characteristics such as 40 dB were not attainable.
In addition, single-pole single-throw (SPST) switches for the 94 GHz band (hereinafter to be referred to as Conventional example 2) were reported by H. Takasu et al. in “IEEE MICROWAVE AND GUIDED LETTERS, Vol. 6, pp. 315–316” and can be nominated, conventionally, as an example of another switch. This switch of Conventional example 2 is also one of possible circuits as switching circuits for high frequency bands not less than 60 GHz.
An SPST switch of Conventional example 2 comprises configuration as shown in FIG. 13. An SPST switch of Conventional example 2 comprises a field effect transistor (FET), an inductor, and a resistance. The input-output terminals 31, 32 are respectively connected with the source and drain of an FET, between which an inductor L configured with a microstrip line pass is connected in parallel. To the gate of FET, a resistance R of 2.5 kΩ is connected, and via the resistance a direct current bias is arranged to be applied to the gate. In the state that the channel of FET is closed, the FET can be treated equivalently as a capacitance C, which, therefore, as shown in FIG. 14, together with the inductance L connected with the FET in parallel, resonance takes place at a frequency obtainable from the equation (3), and as a consequence, resulting in high impedance so that signal propagation between the input-output terminals will be cut off. That is, the switch enters the off state.
                    f        =                  1                      2            ⁢                                                  ⁢            π            ⁢                          LC                                                          (        3        )            
FIG. 15 shows frequency characteristics on insertion loss as well as isolation in the switch of Conventional example 2. As obvious from FIG. 15, in the switching circuit of Conventional example 2, isolation characteristics around 30 dB are attainable with comparatively low insertion loss. However, since, as described before, the switching circuit of Conventional example 2 makes use of resonance, its frequency characteristics will fall in narrow band width. Moreover, for the purpose of making a resonance circuit start resonance at a desired frequency, it is necessary to accurately know LC being a constant of the circuit. Accordingly, for the purpose of using a switch of Conventional example 2, not only the capacitance C to appear at closure of the FET channel will have to be accurately estimated, but also as concerns the inductor L accurate modeling will become necessary. On the contrary, FETs as well as PIN diodes, etc., normally have variation of forming process to a certain extent, but for example, due to this variation, the value of capacitance C could deviate from the design, and as a result the resonance frequency will deviate from the design as well, and resonance will not be available at a desired frequency, which, as a consequence, will give rise to reduction of yield.
Switching circuits (hereinafter to be referred to as Conventional example 3) were conventionally proposed by H. Mizutani and Y. Takayama in “1997 MTT-S IMS Digest pp. 439–442” and can be nominated as technology to solve the problems with the aforementioned Conventional example 1 as well as Conventional example 2. The switching circuit of Conventional example 3 is a switching circuit utilizing an FET showing distributed parameter effect, and its wide band width characteristics were proved in the document. Incidentally, the contents of the document has been disclosed in Japanese Patent Laid-Open No. 10-41404 specification as well.
A switching circuit of Conventional example 3 comprises the configuration as shown in FIG. 16. As understandable with reference to FIG. 16, the switching circuit of Conventional example 3 comprises plural transmission lines and plural FETs. For the switching circuit of Conventional example 3 in detail, each transmission line as well as each FET is respectively defined per micro unit length, and transmission lines are connected in series, and the drain of each FET is connected to the respective junction of them. Incidentally, the source of each FET is connected with the earth. The configuration is made in an infinite connection of these transmission line as well as FET per micro unit length.
Such switching circuit of Conventional example 3 is implemented as a plane surface pattern, where each FET (hereinafter to be referred to as distributed parameter FET) comprises a source connected with the earth, a gate finger with a length of 400 μm, and a drain electrode, both longitudinal ends of which have been connected with the input-output terminals.
A switching circuit of Conventional example 3 comprising such a configuration acts equivalently as a transmission line without any loss as shown in FIG. 17 in the state that the channel of FET is closed. As apparent from FIG. 17, the switch enters the ON state, and insertion loss is expressed by the equation (4) through the equation (6).
                              S          21          ON                =                              2            ⁢                          ZZ              0                                                          2              ⁢                              ZZ                0                            ⁢              cos              ⁢                                                          ⁢              β1                        +                                          j                ⁡                                  (                                                            Z                      2                                        +                                          Z                      0                      2                                                        )                                            ⁢              sin              ⁢                                                          ⁢              β              ⁢                                                          ⁢              1                                                          (        4        )                                β        =                  ω          ⁢                                    (                              L                ⁡                                  (                                                            C                      IL                                        +                                          C                      FET                                                        )                                                                                        (        5        )                                Z        =                              L                          (                                                C                  IL                                +                                  C                  FET                                            )                                                          (        6        )            
Here, “Z” represents impedance of the switch, “1” represents length of a finger of an FET, Z0 represents impedance of the input-output terminal. In addition, “ω” represents angular frequency, and L, R, C, and G respectively represent inductance, resistance, parallel capacitance, parallel conductance per unit length of the switch.
On the other hand, an FET is equivalently expressed as a mere resistance in the state where its channel is open, thus, the equivalent circuit on the switch at that time will be as shown in FIG. 18. As understandable with reference to FIG. 18, a switching circuit of Conventional example 3 acts equivalently as a transmission line with loss in the state that the channel of FET is open, that is, the switch enters the OFF state, and its isolation can be expressed by the equation (7) through the equation (9).
                              S          21          ON                =                              2            ⁢                          ZZ              0                                                          2              ⁢                              ZZ                0                            ⁢              cosh              ⁢                                                          ⁢              ψ                        +                                          (                                                      Z                    2                                    +                                      Z                    0                    2                                                  )                            ⁢              sinh              ⁢                                                          ⁢              ψ                                                          (        7        )                                γ        ≡                  α          +                      j            ⁢                                                  ⁢            β                          ≡                              j            ⁢                                                  ⁢            ω            ⁢                                                  ⁢                          L              ⁡                              (                                                      j                    ⁢                                                                                  ⁢                    ω                    ⁢                                                                                  ⁢                                          C                      IL                                                        +                  G                                )                                                                        (        8        )                                Z        =                                            j              ⁢                                                          ⁢              ω              ⁢                                                          ⁢              L                                                      j                ⁢                                                                  ⁢                ω                ⁢                                                                  ⁢                                  C                  IL                                            +              G                                                          (        9        )            
From these equations, in a wide band as shown in FIG. 19, low insertion loss and high isolation are obtainable. As understandable from FIG. 19, frequency characteristics of isolation in the switching circuit of Conventional example 3 are in gradual increase.
However, not only in switching circuits of the above-described Conventional example 1 as well as Conventional example 2 without doubt, but also in switching circuit of Conventional example 3 it was practically difficult to maintain low insertion loss and realize high isolation in a wide band as a comparatively compact type. This point is explained in detail as follows.
In a switch according to Conventional example 3, the 0th digit term concerning the frequency of isolation is expressed by the equation (10).
                              IL          DC                =                              (                          2                              2                +                                                      Z                    0                                    r                                                      )                    2                                    (        10        )            
As understandable from the equation (10), as resistance “r” of distributed parameter FET gets smaller, isolation gets greater. Incidentally, in the switching circuit using a distributed parameter FET, the 0th digit close resemblance on the isolation frequency corresponds with the isolation of the switching circuit with shunt configuration using a lumped constant FET expressed in the aforementioned equation (2).
Accordingly, for the purpose of attaining high isolation in the switching circuit of Conventional example 3, the gate finger length must be lengthened so that the resistance “r” of distributed parameter FET be reduced. In particular, for the purpose of attaining high isolation of not less than 80 dB in the switching circuit of Conventional example 3, the gate finger length must be lengthened to, for example, 1 mm so that the resistance “r” of distributed parameter FET be reduced. To extend the gate finger length like this means the chip size of microwave or millimeter wave single integrated circuit (MMIC) will get bigger.
As understandable from these features, in microwave or millimeter wave band switching circuits there was a problem that it was difficult for the prior art to realize high isolation of not less than 80 dB covering a wide band width with a comparatively small type configuration, while maintaining low insertion loss. This was originated in circuit configurations in the respective prior arts, such as, existence respectively of the trade-off relationship between insertion loss and isolation, narrow band width characteristics due to usage of resonance, or the trade-off relationship between resistance of distributed parameter FET and the chip size.